Avicena will showcase the world’s smallest 1Tbps optical transceiver at the SuperComputing Conference 2023 in Denver, CO

Avicena is showing the world’s smallest 1Tbps microLED-based transceiver using its LightBundle^TM multi-terabit interconnect technology

SUNNYVALE, Calif.–(BUSINESS WIRE)–#innovation–Avicena, a privately held company headquartered in Sunnyvale, CA, is demonstrating the world’s smallest 1Tbps optical transceiver as part its LightBundle^TM multi-Tbps chip-to-chip interconnect technology at the SuperComputing Conference (SC23) in Denver, CO (https://sc23.supercomputing.org/). Avicena’s microLED-based LightBundle architecture supports unprecedented throughput, shoreline density and low power, unlocking the performance of processors, memory, and sensors.

Artificial intelligence (AI) is driving an unprecedented surge in demand for compute and memory performance, driven by applications like ChatGPT based on large language models (LLMs). These sophisticated models have an insatiable appetite for computing power and fast access to large amounts of memory, resulting in an urgent and growing demand for much higher density low-power interconnects between Graphics Processing Units (GPUs) and high-bandwidth memory (HBM) modules. Today, HBM modules must be co-packaged with GPUs because the GPU-memory electrical interconnect is limited to just a few millimeters in length. Subsequent HBM generations will require IC shoreline densities in the range of 10Tbps/mm or more. Conventional optical interconnects based on VCSELs or Silicon Photonics (SiPh) promise to extend the interconnect reach but struggle to meet size, bandwidth density, power, latency, operating temperature, and cost requirements. By contrast, Avicena’s microLED-based LightBundle interconnects provide higher bandwidth density, much smaller size, much lower power and latency, and very low costs.

“At Avicena we are excited to showcase the world’s most compact 1Tbps transceiver in the shape of a 3mm x 4mm CMOS ASIC using our patented microLED optical interface,” says Bardia Pezeshki, Founder and CEO of Avicena. “Everyone is talking about SiPh solutions for applications in AI clusters. However, for short reach interconnects with less than 10m reach, we believe that our LED based solution is inherently better suited because the compact size, higher bandwidth density, lower power and latency, and temperature tolerance up to 150°C.”

Avicena’s innovations are supported by key investors including Samsung Catalyst Fund, Cerberus Capital Management, Clear Ventures, and Micron Ventures (see press release from August 2^nd, 2022, for more details).

“Optical interconnect technology has the potential to improve chip-to-chip and inter-rack performance,” says Marco Chisari, head of the Samsung Semiconductor Innovation Center. “With a roadmap to multi-Tbps capacity and sub-pJ/bit power efficiency, Avicena’s innovative LightBundle interconnects can enable the next era of AI innovation, paving the way for even more capable models and a wide range of AI applications that will shape the future.”

About the Technology

Today’s high-performance ICs use SerDes-based electrical interfaces to achieve adequate off-chip density. However, the power consumption and bandwidth density of these electrical links degrade quickly with length. Conventional optical communications technologies developed for networking applications have been impractical for inter-processor and processor-memory interconnects due to their size, low bandwidth density, high power consumption, and high cost. The typical need for external laser sources (ELS) with SiPh increases complexity and cost. By contrast the LightBundle^TM interconnect architecture is based on arrays of innovative GaN microLEDs that leverage the microLED display ecosystem and can be integrated directly onto compact high-performance CMOS ICs. This enables dense low-power IO over the entire area of the IC, enabling unprecedented shoreline densities. Each microLED array is connected via a multi-core fiber cable to a matching array of CMOS-compatible PDs.

“We have previously demonstrated microLEDs transmitting at > 10Gbps per lane and a test ASIC in a 130nm CMOS process running 32 lanes at less than 1pJ/bit,” says Rob Kalman, co-founder and CTO of Avicena. “Now we are bringing up our first ASIC with over 300 lanes and an aggregate bandwidth of over 1Tbps bi-directional at 4Gbps per lane. The ASIC measures less than 12mm² and contains a full transceiver including the circuitry for the optical Tx and Rx arrays, as well as a high-speed parallel electrical interface and various DFT/DFM functions like BERT, loopbacks, and Open Eye Monitoring (OEM). All key ASIC functionality has been verified and we are currently working on yield improvements for manufacturing scalability.”

The modular LightBundle platform scales to interconnects with tens of Tbps with a shoreline density > 10Tbps/mm. LightBundle is not tied to any foundry process, allowing it to be integrated onto a wide variety of IC process nodes. The compact size, high density, low power, and low latency of LightBundle is ideal for high-density chiplet interfaces like UCIe, OpenHBI, and BoW, and can also greatly extend the reach of existing compute interconnects like PCIe/CXL, and HBM/DDR/GDDR memory links.

Avicena at SC23:

Avicena will be showcasing its LightBundle interconnect technology at Booth #1791.

About Avicena

Avicena Tech Corp. is a privately held company located in Sunnyvale, CA, developing LightBundle, a next generation optical interconnect architecture for AI/ML, HPC, sensors, 5G wireless and aerospace applications. This unique, flexible ultra-low energy technology is based on microLEDs, offering both very high bandwidth and low latency. Now, system designers can disaggregate functions like compute and memory and radically grow system throughput. Avicena’s technology is a key building block in the evolution of networking and computing that will reduce the energy impact on our planet.

For more information, visit https://avicena.tech

Contacts

Avicena Media Contact:

Sama Pourmojib

email: sama@avicena.tech